PCBs typically comprise discrete semiconductor components to achieve the desired functionality of the PCB. This typically includes a voltage regulator, which is used to provide the various components of the PCB with a constant voltage supply to ensure that these components do not display any undesirable behavior resulting from variations in their voltage supply. The voltage regulator may for instance be designed to convert an alternating current into a direct current.
A popular embodiment of such a voltage regulator or power converter is a pair of serially connected power MOSFETs, which are vertical transistors capable of handling much larger currents than the traditional lateral devices.
A limiting factor in the efficiency of a voltage regulator is the time it takes for the drain current to rise and fall within the power MOSFETs used inside the regulator. For a high current voltage regulator, such as those used in computing applications, which typically handle 10 A-30 A per phase, the loss due to the current rise and fall are larger than the losses due to the QGD of the device, which affects the voltage rise and fall times. The rise and fall times of the current are limited by the source inductance of the control FET, i.e. the high side MOSFET and the total loop inductance, i.e. the inductance path from the input inductor through the two MOSFETs and back to the input inductor.
In order to improve system efficiencies, there is a clear requirement to reduce both package and loop inductance by integrating the two MOSFETs in a single package. The MOSFETs are typically provided on different dies within a single semiconductor package such as a MCM (multi-chip module), with a high side MOSFET having its drain connected to the voltage input and a low side MOSFET having its source connected to ground. Alternatively, the two MOSFETs may be combined with a driver IC (integrated circuit). Such devices are sometimes referred to as DrMOS devices.
In addition to the need to reduce inductance to improve switching speed, the loop inductance is also responsible for generating voltage spikes that can cause problematical EMI, damage to driver and control ICs, and also require higher voltage (i.e. more expensive) power MOSFETs to be used (e.g. for 12V conversion, 30V MOSFETs are standard).
The maximum theoretical di/dt of a half bridge is limited by the formula below, where Ltot represents the total loop inductance of the circuit and is the sum of the PCB and package inductances:
            ⅆ      i              ⅆ      t        =            V      in              L      tot      
The actually achieved switching speed depends on how quickly the high side MOSFET is switched, which is limited by the magnitude of its package inductance, Ls. This is because the source inductance forms part of the gate drive current path and the voltage induced on this inductor acts as a feedback mechanism to reduce switching speed.
In addition to efficiency, voltage overstress is also a concern in devices switching at or close to the theoretical limits. But to the nonlinear capacitance of power MOSFETs voltage spikes can reach 2.5 to 3 times the conversion voltage (so for 12V operation spices in excess of 30V can be achieved). The magnitude of voltage spikes is related to the ratio of source inductance of the high side MOSFET and the total loop inductance. For low spikes Ls needs to be as large a proportion of Ltot as possible.
For optimum performance, it is critical to reduce both Ls and Ltot whilst ensuring that Ls remains a significant proportion of Ltot. With package source inductance being of the order of 0.1 nH in some technologies, the source inductance can be removed completely from the gate drive loop, such that it becomes critical to reduce the magnitude of the PCB inductances to improve both performance and voltage spiking behaviour.
The benefits of reducing PCB inductance by using techniques such as the provision of a bypass capacitor in parallel with the MOSFETs to suppress the voltage surges when the voltage regulator turns on to improve its performance are known per se. The bypass capacitor must be placed in close vicinity to the MOSFETs to minimize parasitic inductance and thus improve the efficiency of the voltage surge suppression. For instance, US 2011/0024884 A1 discloses a power converter semiconductor package in which a high-side MOSFET chip is stacked onto a low side MOSFET chip. The insulation between the top source electrode of the low side MOSFET chip and the bottom drain electrode of the high side MOSFET chip is provided by a vertical capacitor sandwiched between the low side MOSFET chip and the high side MOSFET chip, with the bottom electrode of the capacitor electrically connected to the top source electrode of the low side MOSFET chip and the top electrode of the capacitor electrically connected to the bottom drain electrode of the low side MOSFET chip.
This semiconductor package has a number of notable drawbacks. It is complex to manufacture, thus adding to the cost of the package. In addition, the placement of the capacitor in between the MOSFET chips negatively impacts the current flow between these chips as it increases the metal resistance of the low side MOSFET, thus compromising the performance characteristics of the power converter. Moreover, it is difficult to achieve such a capacitor with a sufficiently large capacitance in an economically feasible manner, as for such lateral capacitors the capacitance scales with A/d where A is the plate area and d is the distance between the plates, i.e. the thickness of the dielectric layer. Not only is A relatively small in lateral devices, but d has to be kept relatively large as the dielectric layer must be thick enough to withstand the mechanical forces associated with bonding the upper die onto the lower die.